IEEE-NANO 2013 Paper Abstract


Paper WeA4.6

Tran, Duy Phu (University of South Australia), Wolfrum, Bernhard (Peter Grünberg Institute, Forschungszentrum Juelich GmbH), Stockmann, Regina (Peter Grünberg Institute, Forschungszentrum Juelich GmbH), Offenhausser, Andreas (Peter Grünberg Institute, Forschungszentrum Juelich GmbH), Thierry, Benjamin (Ian Wark Research institute, University of South Australia)

Wafer-Scale Fabrication of Ultra-Thin Silicon Nanowire Devices

Scheduled for presentation during the Oral Session "Nanoelectronics: Nanotubes and Nanowires I" (WeA4), Wednesday, August 7, 2013, 14:15−14:30, Jade III

13th IEEE International Conference on Nanotechnology, August 5-8, 2013, Shangri-La Hotel, Beijing, China

This information is tentative and subject to change. Compiled on October 15, 2018

Keywords Nanofabrication, Nanoassemblies and devices, Nanosensors and actuators


We present a robust wafer-scale top-down process for the fabrication of locally thinned-downed silicon nanowire (SiNW) devices. The fabrication is based on electron-beam lithography in combination with a two-step tetramethylammonium hydroxide (TMAH) wet etch. We optimized the etching profile of the TMAH process on silicon-on-insulator <100> using isopropanol additive and temperature regulation, yielding very low and controllable etching rates and enabling the formation of ultra-smooth silicon morphology. The optimized TMAH etching process was confined using photolithography to the middle sections of silicon nanowire channels to achieve localized step-etching of the nanowires. The thinned silicon nanowires were addressed via metal contact lines in the final step of the fabrication. Preliminary current-voltage characterization in liquid demonstrated a p-channel field effect transistor behavior in depletion mode with a very high output current and negligible contact resistance. The proposed process provides an alternative route for reliable and reproducible fabrication of ultra-thin silicon nanowire devices.



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