Li, Yiming (National Chiao Tung University), Chen, Chien-Hung (Department of Electrical Engineering, National Cheng-Kung Univer)

Experimentally Effective Clean Process to C-V Characteristic Variation Reduction of HKMG MOS Devices

Scheduled for presentation during the Oral Session "Nanoelectronics: Circuits and Architecture IV" (ThD4), Thursday, August 8, 2013, 17:30−17:45, Diamond II

13th IEEE International Conference on Nanotechnology, August 5-8, 2013, Shangri-La Hotel, Beijing, China

This information is tentative and subject to change. Compiled on July 26, 2021

Abstract

In this work, the planar HKMG MOS devices are fabricated on (100) wafer with p-substrate. To improve the samples’ interface roughness between the Si/Ge film and the interface layer, three different clean treatments are considered to fabricate the MOS devices. Among processes, the experiment indicates that HF and water rinse can present hydrogen termination to bond silicon as a good passivation. The measured C-V curves and HRTEM of the fabricated samples show the interface roughness is improved significantly. The extracted shift of flat band voltage (DVfb) and density of interface traps (Dit) have around 50% improvement.