August 15-18, 2011, Portland, Oregon
  

NANO 2011 Paper Abstract

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Paper ThP2T1.4

Aymerich, Nivard (UPC Barcelona Tech), Cotofana, Sorin (Delft University of Technology), Rubio, Antonio (Universitat Politècnica de Catalunya)

Adaptive Fault-Tolerant Architecture for Unreliable Device Technologies

Scheduled for presentation during the Oral Session "Nanocircuits & Architectures: Reversible Logic & Fault Tolerance" (ThP2T1), Thursday, August 18, 2011, 17:10−17:30, Salon A/B

IEEE NANO 2011 Conference, August 15-18, 2011, Portland Marriott Downtown, Portland, Oregon, USA

This information is tentative and subject to change. Compiled on February 19, 2018

Keywords Nanoelectronics: Nanocircuits, Architectures, Nanoelectronics: Reliability and Yield

Abstract

This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging cell structure (AD-AVG) that is able to cope with non-homogeneous variability and time-varying effects like degradation and external aggressions, which are expected to be a key limiting factor in future technologies. In order to achieve this goal the AD-AVG relies on the modification of the average weights so that reliable inputs have greater influence in the result than less reliable inputs. In this paper we find analytically the distribution of weights that minimizes the probability of error at the output of the cell in terms of the input variability levels. Monte Carlo based simulation results indicate that our proposal outperforms the traditional AVG at the expense of a lower area overhead. For the same reliability target the AD-AVG scheme requires about 70% less redundancy, when compared with the traditional balanced AVG approach.

 

 

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